The present invention is related to circuits in which a field-effect transistor device controls power transfer from an alternating polarity electrical power supply to a load means, particularly when such field-effect transistor devices are capable of being integrated into monolithic integrated circuits.
Various solid state devices have been used in circuits as the primary means for controlling power transfer from an alternating polarity electrical power supply to whatever kind of load means is of interest for use in the circuit. Noting the three above-referenced applications, one of the applications discloses such field-effect transistor devices as are suitable for use as the primary element for controlling power transfer from an alternating polarity electrical power supply to such loads, and the other two show various circuit means for use in conjunction with such field-effect transistor devices to direct operation of these devices. As set out therein, the field-effect transistor device is a device which can provide symmetrical, bidirectional current conducting capability for use in alternating polarity power supply circuits. Particularly useful are devices which are effectively insulated-gate field-effect transistors (IGFET's) often metal-oxide-semiconductor field-effect transistors (MOSFET's), which have the further advantage of having the gate or control regions therein very well isolated from the remaining portions of the device including the channel region and the terminating regions at the ends of the channel region.
Such electrical isolation between the gate or control region, of an IGFET device and its remaining portions aids in providing a control circuit having as its purpose the directing of the operation of this transistor device. This isolation is particularly helpful when the control circuits and the transistor device are formed in a monolithic integrated circuit chip because a difficult control problem can arise when the power supplied to the integrated circuit is from an alternating polarity power supply. Such monolithic integrated circuit configurations must provide for the operation of the primary power transfer control MOSFET device in the control of power transfers from the alternating polarity power supply to the load, while also providing for operation of other circuit components further provided in the monolithic integrated circuit chip.
As is well known, electronic component device theory shows that field-effect transistors are operated by controlling the voltage appearing between the gate thereof and the connection to that one of the two channel terminating regions therein which is effectively serving as the transistor source. Difficulties arise in those circuits using a field-effect transistor control power transfers from an alternating polarity power supply to a load means because the two connections to the channel region of such a device serve alternately as source connections rather than one of them serving continually as the source connection.
FIG. 1 shows an abbreviated version of a circuit disclosed in the control circuit application referenced above having the largest serial number. This circuit uses what is effectively an enhancement mode, p-channel, IGFET, 10, for controlling power transfers from alternating polarity electrical power supply, 11, to a load means, 12, or alternatively to a load means, 12', shown in dashed lines. Device 10 can be a device of the nature disclosed in the application referenced above having the smallest serial number.
An advantage of the circuit shown in FIG. 1 herein is that the circuitry for controlling power transfers through transistor 10 from supply 11 to load means 12 can be operated from electrical power supplied solely by alternating power supply 11. That is, a control switch means, 33, is shown for operating transistor 10. Control switch means 33 can be operated solely from voltage developed across a capacitor, 27, connected to substrate 13 of transistor 10, this voltage being derived ultimately from supply 11. Further advantages in the circuit of FIG. 1 come about because of the provision of several bypass transistors, 40, 41, and 42, which shunt certain parasitic circuit components associated with transistor device 10, and which thereby permit operating the circuit of FIG. 1 at higher polarity alternation frequencies in power supply 11 than would otherwise be possible.
These transistor 10 associated circuit components which affect circuit operation, but are only parasitic components inherent in transistor 10, are presented in equivalent "lumped" form and are shown by dashed lines in FIG. 1, they again all being present as the result of the actual physical structure of transistor 10. Of course, every transistor physical structure leads to having, effectively, parasitic circuit components associated therewith. However, such parasitic components are more likely to be significant in value for a power control transistor device, such as transistor 10, compared to signal control transistors because the power transistors usually are of a relatively large physical size when compared to transistors used for controlling signals only. Thus, parasitic components are explicitly shown associated only with transistor 10 in FIG. 1 even though parasitic components are also associated with the structures of the other transistors shown in FIG. 1. The assumption is that in practice, these other transistors have associated parasitic components that would have a relatively insignificant effect on the operation of the circuit in FIG. 1.
Field-effect transistor 10, being a p-channel IGFET, is provided in and on a substrate, 13, of a semiconductor material of n-type conductivity. The channel connection or terminating regions, 15 and 16, which terminate the ends of the channel region (when a channel is induced) in transistor 10 and can serve as source and drain regions therein, are formed by diffusion or implantation of p-type conductivity impurities into the substrate material. Parasitic diodes are formed in the structure of transistor 10 by the semiconductor pn junctions occurring between regions 15 and 16, on the one hand, and a substrate of transistor 10 on the other. These diodes are designated 17 and 18 in FIG. 1.
Also associated with these pn junctions are parasitic capacitances, 19 and 20, and parasitic resistances, 21 and 22. Further parasitic capacitances present are a channel-to-substrate capacitance, 23, and a gate-to-channel capacitance, 24. Two other parasitic capacitances, 25 and 26, are shown which are effective between gate 14 and one of the channel terminating regions 15 or 16. All of these parasitic components will have more or less of an effect on the operating behavior of transistor 10, and so in the behavior of the circuit in which transistor 10 is provided. The significance of the effects depends on the conditions existing in such a circuit and the values of the parasitic components. Of course, capacitance 24 is essential for switching on transistor 10 through forming a channel, yet this capacitance and the other parasitic component shown with transistor 10 are normally desired to contribute as insignificantly as possible to the circuit operation.
At sufficiently low frequencies, the parasitic capacitance as shown in connection with transistor 10 in FIG. 1 will not be significant factors in the operation of the circuit of this figure. Also, the leakage resistances 21 and 22 of FIG. 1 are usually sufficiently large so that they will not be significant in the operation of this circuit.
Further, note that load means 12 could also have a reactance component thereto, but this has not been shown, and load means 12 will be described as being resistive for ease of understanding and exhibition. This is also true of the alternative to load means 12, that is load means 12'. Load means 12' can be used in place of load means 12 with similar operating results in the circuit of FIG. 1 because of the symmetry inherent therein. This point is mentioned in the above referenced control circuit.
In FIG. 1, there are two diodes, 28 and 29, connected across alternating polarity power supply 11. Diode 28 has its cathode connected to a circuit portion including alternating polarity power supply 11 and load means 12, and has the anode thereof connected to energy storage capacitor 27. The anode of diode 29 is also connected to energy storage capacitor 27. The cathode of diode 29 is connected to power supply 11, i.e. again to the circuit portion arrangement including supply 11 and load means 12. As indicated in the above-referenced applications involving control apparatus, several of the transistors in the circuit of FIG. 1 can each have its substrate connection electrically connected in common with each of the other transistors as would occur if they were jointly formed in a single monolithic integrated circuit chip. Circumstances in which this is possible are indicated or referenced in the patent applications just mentioned.
As indicated above, the sole source of power used to operate the circuit of FIG. 1 is alternating polarity supply 11. Supply 11 not only provides power for controlled transfer to load means 12 (the load chosen for the following description of the FIG. 1 circuit operation), upon being selected to do so by appropriately activating switching means 33, but also provides power to be stored in capacitor 27 to operate the circuitry of switching means 33 and perhaps other circuits. Of course, a separate power supply means could be used in place of capacitance 27, and this is done to use a depletion mode device in place of enhancement mode transistor 10 as indicated in the above referenced control circuit applications. Hence, in the arrangement of FIG. 1, with constant polarity voltage being supplied to switching means 33 from across capacitor 27, a pair of transistors, 34 and 35, explicitly shown as part of switching means 33 and the associated switch control circuitry, 36, are all electrically energized by the stored electrical energy provided in capacitor 27. When being operated, switch means 33 has either transistor 34 in the "on" condition and transistor 35 "off," or vice versa, as determined by switch control circuitry 36. As a result, transistors 34 and 35 together operate in series as a single pole, double throw switch.
In the operation of the FIG. 1 circuit, the two channel connection, or termination, regions 15 and 16 of transistor 10 alternately serve as source and drain, depending on which one is positive with respect to the other in a cycle of the output voltage provided by supply 11. Consider switch means 33 electrically connecting gate 14 to the side of capacitor 27 connected to substrate 13. In this switch selection for switch means 33, gate 14 of transistor 10 will approximately be at the positive voltage appearing on one or the other side of supply 11 alternately during a cycle by virtue of one of diodes 17 or 18 correspondingly being forward biased. Also correspondingly, one of the diodes 28 or 29 will be forward biased. In this situation, substrate 13 is forced to be at the voltage supplied at whichever of terminating regions 15 or 16 is positive less the voltage drop across the associated one of forward biased diodes 17 or 18. The other of diodes 17 or 18, associated with the transistor 10 terminating region serving as the drain, will be reverse biased.
The voltage drop across either of diodes 17 or 18, when forward biased, will always be less than the threshold voltage of transistor 10. Since gate 14 will, in these circumstances, never be more than approximately the voltage drop across one of diodes 17 or 18 from the voltage appearing at that one of terminating regions 15 or 16 which is positive, gate 14 will never differ in voltage from the terminating region serving as a source by an amount equal to the threshold voltage of transistor 10, i.e. transistor 10 will be in the "off" condition according to device theory. There will thus be no power transfer from supply 11 to load means 12.
As a result of this the above switch selection for switch means 33, assuming first that the side of supply 11 connected to load means 12 is relatively positive with respect to the other side of supply 11, a small charging current will flow through load means 12, parasitic diode 17, capacitor 27, and diode 29 to thereby charge capacitor 30. This assumes, initially, that the parasitic component shunting transistors 40, 41, and 42 are not present in the circuit of FIG. 1. The following change in polarity of supply 11, again assuming the omission of transistors 40, 41, and 42, leads to a comparable charging current flowing through parasitic diode 18, capacitor 27, and diode 28 to thereby again charge capacitor 30 to the same polarity as occurred during the charging in the previous half cycle of supply 11. In these circumstances, the polarity of the voltage across capacitor 30 in such that the side of capacitor 30 connected to substrate 13 is positive. Also, the voltage developed across capacitor 27 will substantially be equal to the peak value of the positive voltage supplied alternately at the sides of supply 11.
In the opposite switch selection of switch means 33, gate 14 of transistor 10 will be electrically connected to the side of capacitor 27 not connected to substrate 13. As a result, the voltage between gate 14 and whichever of terminating regions 15 and 16 is positive, and therefore acting as the transistor source, will be equal to whatever voltage is across capacitor 27 plus the corresponding parasitic diode voltage drop. In the usual situation, transistor 10 will have been in the "off" conditon, as just described, and so the voltage across capacitor 27 will be approximately the voltage supplied by supply means 11 as noted above. In this case, and in the usual case, the voltage in capacitor 27 will substantially exceed the threshold voltage of transistor 10 so that transistor 10 will be switched to the "on" condition. Transistor 10 will remain in the "on" condition for this connection of switch means 33 so long as the voltage across capacitor 27 remains greater than the threshold voltage of transistor 10.
In contrast to the situation described above with transistor 10 in the "off" condition, capacitor 27 does not experience similar charging actions in alternate half cycles of a supply 11 cycle if transistor 10 is in the "on" condition assuming, again, that transistors 40, 41, and 42 are initially omitted in the circuit of FIG. 1. If the side of supply 11 not connected to load means 12 is positive, capacitor 27 will be charged by a charging current flowing through parasitic diode 18, capacitor 27, and diode 28 which tends to charge capacitor 27 to a voltage of the same polarity as would occur in charging capacitor 27 with transistor 10 in the "off" condition. This charging occurs because most of the voltage being supplied from supply 11 will be dropped across capacitor 27 and diode 28 approximately in parallel with load means 12 so that there is a substantial voltage across capacitor 27 in this polarity of supply 11.
But, in the opposite polarity of supply 11 with the side thereof connected to load means 12 being positive, no charging current will flow through capacitor 27. With most of the voltage of supply 11 being dropped across load means 12 there will not be any significant voltage applied across capacitor 27. Parasitic diodes 17 and 18 and diode 28 will all be reverse biased. In this situation the electrical energy for operating switching means 13 must be supplied entirely by energy stored on capacitor 27.
The presence of the parasitic components associated with transistor 10 leads to detrimental effects occurring in the operation of the circuit shown in FIG. 1 in the absence of the bypass means provided there as indicated in the above-identified application having the largest serial number. The charging current for capacitor 27 which passes through parasitic diodes 17 and 18 of transistor 10 in the "off" condition can result in bipolar transistor action occurring between terminating regions 15 and 16 of transistor 10. This is because these regions and the channel region form an effective pnp transistor which tends to provide a more or less conductive pathway between terminating regions 15 and 16 otherwise intended to be electrically isolated from one another in these circumstances. Also, the charge on the parasitic capacitances associated with transistor 10 may lead to delays in the intended operation of the various regions of transistor 10 because the charged parasitic capacitances tend to maintain earlier existing conditions about transistor 10 until these parasitic capacitances have been discharged. To circumvent such detrimental effects in the operation of the circuit of FIG. 1 of the present application, several bypass transistors are provided in the circuit of FIG. 1 for reducing or eliminating certain of these effects resulting from the parasitic components associated with transistor 10.
The three bypass transistors are designated 40, 41, and 42 in FIG. 1 and are shown as enhancement mode, p-channel, field-effect transistors. They may also be fabricated in a single integrated monolithic circuit chip along with transistor 10, the circuitry of switch means 33, etc. as described in the above-referenced application having the largest serial number. Bypass transistors 40, 41 and 42 are affected in reducing or eliminating the effects of the parasitic components associated with transistor 10 only when transistor 10 is in the "off" condition.
In operation, with transistor 10 being in the "off" condition by virtue of switch means 33 electrically connecting gate 14 to substrate 13, a small current for charging capacitor 27 alternately flows through transistors 40 and 41, as a result of their switching on and off in response to the polarity changes in supply 11, rather than through parasitic diode 17 and 18, respectively, of transistor 10 in the circuit operation described above. Reducing or eliminating current flow through parasitic diode 17 and 18 serves to substantially eliminate bipolar action in transistor 10 between terminating regions 15 and 16 and the channel region thereof. This reduction in current flow also results in improved frequency response of the circuit containing transistor 10 because transistors 40 and 41 provide low impedance discharge paths for certain of the parasitic capacitances therein.
Transistor 42 shunts gate-to-source capacitance 25 during one polarity of supply 11 to thereby improve frequency response and prevent loss of control of transistor 10 due to an accumulation of charge in this capacitance during operation times in which transistor 10 in the "off" condition. In the alternate half cycle of supply 11, i.e. the opposite polarity of supply 11, capacitance 26 is effectively shunted by transistor 41 and transistor 34 which are both in the "on" condition. Transistor 42 is off and has no effect on circuit operation in this condition.
However, when transistor 10 is switched by switching means 33 to the "on" condition, bypass transistors 40, 41 and 42 of the circuit of FIG. 1 become ineffective. The voltage drop between terminating regions 15 and 16 of transistor 10 is less than the threshold voltage of any of the transistors 40, 41 and 42 and FIG. 1 shows that this voltage drop across transistor 10 is also the voltage drop occuring between the gate and the effective source of transistors 40, 41, and 42. Thus, transistors 40, 41, or 42 are all switched to the "off" condition in the circuit of FIG. 1 when transistor 10 is in the "on" condition.
Thus, operation of the circuit of FIG. 1 when transistor 10 is in the "on" condition occurs just as described above for FIG. 1 when it was assumed that transistors 40, 41, or 42 were omitted in that FIG. 1. In one polarity of supply 11, a small charging current will flow to charge capacitor 27, the current flowing through a parasitic diode 18, capacitor 27, and diode 28. This occurs because the voltage of supply 11 is dropped across capacitor 27 and diode 28 connected approximately in parallel with load means 12. This current flowing through parasitic diode 18 will cause bipolar action between terminating regions 15 and 16 by virtue of the effect of pnp transistor present there as described above. If there is a desire to switch transistor 10 to the "off" condition, the bipolar action of the effective pnp transistor will tend to keep transistor 10 conducting, thus resulting in reduced control of transistor 10.
In the other half cycle of a cycle of supply 11, parasitic diodes 17 and 18 are reversed bias because of the voltage remaining on capacitor 27. As a result, substrate 13 of transistor 10 and capacitance 27 are not firmly related to any voltage occuring in the circuit of FIG. 1. In this situation, the parasitic capacitances of transistor 10, particularly capacitances 19 and 20, can accumulate a random amount of charge supplied by either supply 11 or capacitor 27 or both. This random accumulation of charge obtained on these parasitic capacitances causes the voltage on substrate 13 to vary randomly with respect to whichever terminating regions 15 and 16 is serving as a source. Such a situation may be reflected in a random variation of the threshold voltage of transistor 10 as well as in the threshold voltages of the other transistors shown in FIG. 1 which have their substrates, selectively, in common with transistor 10 as is the case when all these transistors are formed in the same monolithic integrated circuit chip.
For example, transistors 34 and 35 of switch means 33 and the transistors in the switch control circuitry 36 of switch means 33 will often be formed in the same monolithic integrated circuit chip as is transistor 10 and thereby share a common substrate. Thus, the switching on of transistor 10 leading to charging current flowing through parasitic diode 18 may cause the threshold voltages of the transistors in switch means 33 to vary randomly in a manner which could result in loss of control of transistor 10.
Further, random accumulation of charge in the parasitic capacitances associated with transistor 10 may also lead to additional delays in the intended operation of transistor 10 as the charged parasitic capacitances tend to maintain earlier conditions occurring about transistor 10 until these capacitances have been discharged. This can result in transistor 10 responding slowly, incompletely, or not at all to commands provided by switch means 33.